The present invention relates to technology effectively applied to an address management method in an electrically writable and erasable nonvolatile semiconductor storage device. Still, the present invention relates to technology effectively applied to a storage device such as, e.g., a memory card incorporating a flash memory having plural banks from which data can be erased collectively in a predetermined unit.
Recently, as data storage media of portable electronic equipment such as digital cameras, card-type storage devices called memory cards have become widely used. The memory cards incorporate a nonvolatile memory such as a flash memory capable of holding stored data even if power is turned off. Most of the memory cards generally incorporate a nonvolatile memory and a controller to control the writing and reading of data to and from the nonvolatile memory.
A flash memory incorporated in conventional memory cards, which generally has one memory array, is configured to perform writing in a unit (hereinafter referred to as a block) of a memory cell group connected to an identical word line within the memory array (Patent Publication 1). Therefore, the controller to control the writing and reading of data to and from such a flash memory manages addresses on a block basis.
There is an increasing demand for larger-capacity semiconductor memories. Although one method for achieving large-capacity semiconductor memories is to increase the number of memory cells forming one memory array, there is a problem in that bit lines and word lines become longer, resulting in longer data read time. On the other hand, there is a method (multi-bank method) of achieving large-capacity semiconductor memories by providing plural memory arrays (hereinafter referred to banks) within one chip.
Such a multi-bank method is advantageous in that data read time can be reduced because bit lines and word lines within banks do not become so long, and write time and erase time can be reduced because write operation or erase operation is performed in parallel among plural banks.
[Patent Publication 1]
Japanese Unexamined Patent Publication No. 2002-197876